The present invention relates to semiconductor devices, and more particularly, to a delay circuit and a semiconductor device including the delay circuit.
Delay circuits which are widely used in semiconductor devices are generally implemented using complementary metal oxide semiconductor (CMOS) inverters. The term “minimum feature size” used in the field of semiconductor devices refers to the minimum length of lines in semiconductor devices according to the design rules for semiconductor manufacturing processes.
With the development of semiconductor technology, the minimum feature size has been decreased to 180 nm, 90 nm, and 65 nm, and thus a gate length has decreased to the minimum feature size. The decrease of the minimum feature size may change the characteristics of the semiconductor devices. In particular, the characteristics of transistors of CMOS inverters largely vary according to gate length variations. Generally, polysilicon is used for the gate of CMOS inverters. To reduce characteristics variations of the transistors, pitches of polymers applied on the gate need to be uniformly controlled.
A delay circuit, such as a hold buffer which may be generally used for a semiconductor device, includes at least one CMOS inverter and should have a long delay time. Accordingly, even though the gate length of circuits generally used for semiconductor devices has the minimum feature size, the delay time of circuits which require a long delay time, such as the hold buffer, can be increased by increasing the gate length. However, since the gates of circuits of the semiconductor device have different lengths, it becomes difficult to uniformly control the pitch of polymers. Thus, the characteristics of the transistors may be changed.
FIG. 1 shows the layout of a conventional inverter 10. The conventional inverter 10 includes a line supplying a supply voltage VDD, a line supplying a ground voltage VSS, a PMOS transistor formed in an active region 12_1 in the vicinity of the line supplying the supply voltage VDD, and an NMOS transistor formed in an active region 12_2 in the vicinity of the line supplying the ground voltage VSS. Polymer lines 11_1 to 11_3 include a gate line 11_1 and dummy polymer lines 11_2 and 11_3.
A source electrode of the PMOS transistor may be connected to a metal line supplying a supply voltage VDD through a via hole, and a drain electrode of the PMOS transistor may be connected to a metal line supplying an output signal through a via hole. In addition, a source electrode of the NMOS transistor may be connected to a metal line supplying a ground voltage VSS through a via hole, and a drain electrode of the NMOS transistor may be connected to a metal line supplying an output signal through a via. A metal line supplying an input signal may be connected the gate line 11_1 through a via hole.
Since the gate length of the inverter shown in FIG. 1 has the minimum feature size, characteristics of the transistors may not be largely changed due to uniform intervals between polymer lines even though delay time is minimized. However, to increase the delay time when the gate length has the minimum feature size, the inverter needs to have a plurality of stages. Thus, the number of circuits has to be increased and also the area of the inverter has to be increased.
FIG. 2 shows a layout of a conventional inverter 20 having a long delay time. The inverter 20 has a gate line length larger, for example, twice larger, than the gate line 11_1 of the inverter 10 shown in FIG. 1, and the dummy polymers 21_2 and 21_3 of the inverter 20 have the same minimum feature size. In addition, an active width of active regions 22_1 and 22_2 of the inverter 20 is smaller than that of the inverter 10.
That is, in the case of the inverter 20, the delay time can be increased by increasing the length of the gate line 21_1 and decreasing the active width of the active regions 22_1 and 22_2. However, since the pitch of the polymers is not maintained constant as the length of the gate line 21_1 of the inverter 20 is increased, the characteristics of the transistors become changed.